An integrated circuit (IC) is formed by creating one or more devices (e.g., circuit components) on a semiconductor substrate using a fabrication process. As fabrication processes and materials improve, semiconductor device geometries have continued to decrease in size since such devices were first introduced several decades ago. For example, current fabrication processes are producing devices having feature sizes (e.g., the smallest component (or line) that may be created using the process) of less than 90 nm. However, the reduction in size of device geometries frequently introduces new challenges that need to be overcome.
As microelectronic devices are scaled below 45 nm, the electrical efficiency and become an issue that impacts device performance. Microelectronic device performance can be significantly affected by the electron and hole mobility in semiconductor materials. For example, advanced microelectronic devices may incorporate strained silicon as the substrate. Strained silicon comprises a plurality of layers to provide a lattice mismatch of silicon atoms and other atoms such as germanium. The lattice mismatch can provide enhanced improvement of the electron and/or hole mobility of the microelectronic device, thus a reduction in the threshold voltage may be required for a field effect transistor on strained silicon. However, the plurality of layers that form the strained silicon may not provide optimal device operation for all microelectronic devices of a semiconductor product. For example, NMOS devices and PMOS devices can have differing electrical characteristics when fabricated on strained silicon. The differences in the electrical characteristics mandate modification of either the NMOS and/or the PMOS device on strained silicon.
Accordingly, what is needed in the art is an integrated circuit device and method of manufacturing the integrated circuit device that addresses the above discussed issues.